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L9903
MOTOR BRIDGE CONTROLLER
s s s s s s s s s
OPERATING SUPPLY VOLTAGE 8V TO 20V, OVERVOLTAGE MAX. 40V OPERATING SUPPLY VOLTAGE 6V WITH IMPLEMENTED STEPUP CONVERTER QUIESCENT CURRENT IN STANDBY MODE LESS THAN 50A ISO 9141 COMPATIBLE INTERFACE CHARGE PUMP FOR DRIVING A POWER MOS AS REVERSE BATTERY PROTECTION PWM OPERATION FREQUENCY UP TO 30KHZ PROGRAMMABLE CROSS CONDUCTION PROTECTION TIME OVERVOLTAGE, UNDERVOLTAGE, SHORT CIRCUIT AND THERMAL PROTECTION REAL TIME DIAGNOSTIC
SO20 ORDERING NUMBER: L9903
DESCRIPTION Control circuit for power MOS bridge driver in automotive applications with ISO 9141bus interface.
BLOCK DIAGRAM
VS 10
R CP
ST
1
+ =V STH
Ref erence BIAS
VCC Charge pump
11 13
CP CB1 GH1
f ST
12
VCC
Overvoltage Undervoltage Thermal shutdown
RDG
14
S1
DG
2
Control Logic
V S1TH
=
R S1
EN
4
REN
19
R GL1
GL1
18
R GL2
GL2
DIR
5
RDI R VCC
17
R PWM
S2
PWM
3
V S2TH = R S2
PR
6
Timer
15
16
GH2
CB2
ISO-Interface
RX
7
R RX VCC R TX I KH = 0.5 * V VS
9
K
TX
8
20
GND
September 2002
1/17
L9903
PIN FUNCTION
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Pin ST DG PWM EN DIR PR RX TX K VS CP GH1 CB1 S1 GH2 CB2 S2 GL2 GL1 GND Open Drain Switch for Stepup converter Open drain diagnostic output PWM input for H-bridge control Enable input Direction select input for H-bridge control Programmable cross conduction protection time ISO 9141 interface, receiver output ISO 9141 interface, transmitter input ISO 9141 Interface, bidirectional communication K-line Supply voltage Charge pump for driving a power MOS as reverse battery protection Gate driver for power MOS highside switch in halfbridge 1 External bootstrap capacitor Source/drain of halfbridge 1 Gate driver for power MOS highside switch in halfbridge 2 External bootstrap capacitor Source/drain of halfbridge 2 Gate driver for power MOS lowside switch in halfbridge 2 Gate driver for power MOS lowside switch in halfbridge 1 Ground Description
PIN CONNECTION (Top view)
ST DG PWM EN DIR PR RX TX K VS
1 2 3 4 5 6 7 8 9 10
SO20
20 19 18 17 16 15 14 13 12 11
GND GL1 GL2 S2 CB2 GH2 S1 CB1 GH1 CP
2/17
L9903
ABSOLUTE MAXIMUM RATINGS
Symbol VCB1 , VCB2 Bootstrap voltage ICB1 , ICB2 VCP ICP Bootstrap current Charge pump voltage Charge pump current Parameter Value -0.3 to 40 -100 -0.3 to 40 -1 -0.3 to 7 Unit V mA V mA V
VDIR ,VEN Logic input voltage ,VPWM ,VTX IDIR ,IEN ,IPWM ,ITX VDG ,VRX IDG ,IRX Logic input current
1
mA
Logic output voltage Logic output current
-0.3 to 7 -1 -0.3 to VSX + 10 -1 -0.3 to 10 -10 -20 to VS -0.3 to 7 -1 -2 to VVS + 2 -10 -0.3 to 40 -1 -0.3 to 27 40 -10
V mA V mA V mA V V mA V mA V mA V V mA
VGH1, VGH2 Gate driver voltage IGH1 , IGH2 Gate driver current
VGL1 , VGL2 Gate driver voltage IGL1 , IGL2 VK VPR IPR VS1 , VS2 IS1 , IS2 VST IST VVSDC VVSP IVS Gate driver current K-line voltage Programming input voltage Programming input current Source/drain voltage Source/drain current Output voltage Step up output current DC supply voltage Pulse supply voltage (T < 500ms) DC supply current
For externally applied voltages or currents exceeding these limits damage of the device may occur! All pins of the IC are protected against ESD. The verification is performed according to MIL883C, human body model with R=1.5k, C=100pF and discharge voltage 2kV, corresponding to a maximum discharge energy of 0.2mJ.
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L9903
THERMAL DATA
Symbol TJ TJSD TJSDH Rth j-amb Parameter Operating junction temperature Junction temperature thermal shutdown threshold Junction thermal shutdown hysteresis Thermal resistance junction to ambient 1) Value -40 to 150 min 150 typ 15 85 Unit C C C C/W
1. see application note 110 for SO packages.
ELECTRICAL CHARACTERISTCS (8V < VVS < 20V, VEN = HIGH, -40C TJ 150C, unless otherwise specified. The voltages are refered to GND and currents are assumed positive, when current flows into the pin.
Symbol Supply (VS) VVS OVH VVS OVh VVS UVH VVS UVh IVSL IVSH Overvoltage disable HIGH threshold Overvoltage threshold hysteresis 2) Undervoltage disable HIGH threshold Undervoltage threshold hysteresis 2) Supply current Supply current, pwm-mode V EN = 0 ; VVS = 13.5V; T J< 85C VVS= 13.5V; VEN= HIGH; VDIR= LOW; S1 = S2 = GND fPWM = 20kHz; C CBX = 0.1F; CGLX = 4.7nF; CGHX = 4.7nF; RPR = 10k; CPR = 150pF IVSD Supply current, dc-mode VVS= 13.5V; VEN= HIGH; VDIR= LOW; S1 = S2 = GND VPWM = LOW; CGHX = 4.7nF RPR = 10k; CPR = 150pF Enable input (EN) VENL VENH VENh REN Low level High level Hysteresis threshold 2) Input pull down resistance VEN = 5V 16 3.5 1 50 100 1.5 V V V k 5.8 10 mA 8.1 6 0.66 50 13 20 22 1.6 7 24 V V V V A mA Parameter Test Condition Min. Typ. Max. Unit
H-bridge control inputs (DIR, PWM) VDIRL VPWML VDIRH VPWMH VDIRh VPWMh Input low level Input high level Input threshold hysteresis 2) 3.5 1 1.5 V V V
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L9903
ELECTRICAL CHARACTERISTICS (continued)
Symbol RDIR RPWM Parameter Internal pull up resistance to internal VCC 3) Test Condition VDIR = 0; VPWM = 0 Min. 16 Typ. 50 Max. 100 Unit k
DIAGNOSTIC output (DG) VDG RDG Output drop Internal pull up resistance to internal VCC 3) IDG = 1mA VDG = 0V 10 20 0.6 40 V k
Programmable cross conduction protection 4) NPR IPR Threshold voltage ratio VPRH/ VPRL Current capability RPR = 10k VPR = 2V 1.8 -0.5 2 2.2 mA
ISO interface, transmission input (TX) VTXL VTXH VTXh RTX Input low level Input high level Input hysteresis voltage 2) Internal pull up resistance to internal VCC 3) VTX = 0 10 3.5 1 20 40 1.5 V V V k
ISO interface, receiver output (RX) VRXL RRX RRXON tRXH tRXL Output voltage high stage Internal pull up resistance to internal VCC 3) ON resistance to ground Output high delay time Output low delay time TX = HIGH; IRX = 0; VK = VVS TX = HIGH; VRX = 0V TX = LOW; IRX = 1mA Fig. 1 4.5 5 10 40 0.5 0.5 5.5 20 90 V k s s
ISO interface, K-line (K) VKL VKH VKh IKH RKON IKSC fK Input low level Input high level Input hysteresis voltage 2) Input current ON resistance to ground Short circuit current Transmission frequency
2. not tested in production: guaranteed by design and verified in characterization 3. Internal VVCC is 4.5V ... 5.5V 4. see page 18 for calculation of programmable cross conduction protection time
-20V 0.55 * VVS 0.025* VVS V TX = HIGH VTX = LOW; IK=10mA VTX = LOW 40 60 100 -5 10
0.45 * VVS VVS 0.8V 25 30 130 A mA kHz
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L9903
ELECTRICAL CHARACTERISTICS (continued)
Symbol tKr Rise time Parameter Test Condition VVS = 13.5V; Fig. 1 External loads at K-line: RK = 510 pull up to VVS CK = 2.2nF to GND tKf tKH tKL tSH Fall time Switch high delay time Switch low delay time Short circuit detection time VVS = 13.5V; TX = LOW VK > 0.55 * VVS 10 2 4 4 6 17 17 40 s s s s Min. Typ. 2 Max. 6 Unit s
Charge pump VCP Charge pump voltage V VS = 8V VVS = 13.5V VVS = 20V ICP tCP fCP Charging current VCP= VVS + 8V Charging time 2) VCP= VVS + 8V Charge pump frequency VVS = 13.5V VVS = 13.5V CCP = 10nF V VS = 13.5V 250 VVS+ 7V VVS+ 10V VVS+ 10V -50 -75 1.2 500 4 750 VVS+ 14V VVS+ 14V VVS +14V A ms kHz
Drivers for external highside power MOS VCB1 VCB2 RGH1L RGH2L Bootstrap voltage V VS = 8V; ICBX = 0; VSX = 0 VVS =13.5V; ICBX = 0; VSX = 0 VVS = 20V; ICBX = 0; VSX = 0 VCBX = 8V; VSX = 0 IGHX = 50mA; T J = 25C VCBX = 8V; VSX = 0 IGHX = 50mA; T J = 125C RGH1H RGH2H VGH1H VGH2H ON-resistance of SOURCE stage Gate ON voltage (SOURCE) IGHX = -50mA; TJ = 25C IGHX = -50mA; TJ = 125C VVS= VSX = 8V; IGHX = 0; CCBX = 0.1F VVS = VSX = 13.5V; IGHX = 0; CCBX = 0.1F VVS = VSX = 20V; IGHX = 0; CCBX = 0.1F RGH1 RGH2 RS1 RS2 Gate discharge resistance Sink resistance EN = LOW VVS +6.5V VVS+ 10V VVS +10V 10 10 100 100 7.5 10 10 14 14 14 10 V V V
ON-resistance of SINK stage
20
10 20 VVS +14V VVS +14V VVS +14V
k k
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L9903
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Drivers for external lowside power MOS RGL1L RGL2L RGL1H, RGL2H VGL1H, VGL2H RGL1 RGL2 ON-resistance of SINK stage ON-resistance of SOURCE stage Gate ON voltage (SOURCE) IGLX = 50mA; TJ = 25C IGLX = 50mA; TJ = 125C IGLX = -50mA; TJ = 25C IGLX = -50mA; TJ = 125C VVS = 8V; IGLX = 0 VVS = 13.5V; IGLX = 0 VVS = 20V; IGLX = 0 EN = LOW 7V 10V 10V 10 100 10 20 10 20 VVS VVS 14V k
Gate discharge resistance
2. not tested in production: guaranteed by design and verified in characterization
Timing of the drivers tGH1LH tGH2LH Propagation delay time Fig. 2 VVS = 13.5V VS1 = VS2 =0 CCBX = 0.1F RPR= 10kW tGH1LH tGH2LH tGH1HL tGH2HL Propagation delay time including cross conduction protection time tCCP Propagation delay time Fig. 2 VVS = 13.5V VS1 = VS2 =0 CCBX = 0.1F CPR= 150pF; RPR= 10k; 5) Propagation delay time Fig. 2 VVS = 13.5V VS1 = VS2 =0 CCBX = 0.1F RPR= 10k tGL1LH tGL2LH tGL1HL tGL2HL Propagation delay time including cross conduction protection time tCCP Propagation delay time Fig. 2 VVS = 13.5V VS1 = VS2 =0 CCBX = 0.1F CPR= 150pF; RPR= 10k; 5) Rise time Fall time Rise time Fall time Fig. 2 VVS = 13.5V VS1 = VS2 =0 CCBX = 0.1F CGHX = 4.7nF CGLX = 4.7nF RPR= 10k; 1 1 1 1 s s s s 0.7 1 1.3 s 500 ns 0.7 1 1.3 s 500 ns
500
ns
tGL1LH tGL2LH
500
ns
tGH1r tGH2r tGH1f tGH2f tGL1r tGL2r tGL1f tGL2f
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L9903
ELECTRICAL CHARACTERISTICS (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
Short Circuit Detection VS1TH VS2TH tSCd Threshold voltage Detection time (5.2V VVS < 10V) 10 1 2 20 V V 5 4 10 15 V s
Step up converter (ST) VSTH VSTh RDSON
ST disable HIGH threshold ST disable threshold hysteresis voltage 2) Open drain ON resistance VVS = 5.2V; IST = 50mA 50 100
fST
Clock frequency
149
kHz
2. not tested in production: guaranteed by design and verified in characterization 5. tested with differed values in production but guaranteed by design and verified in characterization
8/17
L9903
Figure 1. Timing of the ISO-interface
VTX
0.7 * V V C C
0.3 * V V C C 0.3 * V V C C t V K
t KL tKf t KH t Kr
80 %
0.55 * V V S 0.45 * V V S
2 0%
IK > I K SC
t VR X
t RXL t RXH
0.7 * V VC C
0.3 * V V C C
t
op en d r ain tr ans is to r at K-p in t SH
ON
OFF
Figure 2. Timing of the drivers for the external MOS regarding the inputs DIR and PWM
PWM or DIR
50%
tGHXLH
tGHXr
t GHXHL tGHXf
t
80%
GHX
20%
tGLXHL tGLXf tGLXLH tGLXr
t
80%
GLX
20% t
9/17
L9903
Figure 3. I(V) characteristics of the K-Line for TX = HIGH and VVS=13.5V
IK [mA] 0.2 0.1 0.0 -0.1 -0.2 -0.3 -0.4 -0.5 -20 -10 0 VK [V] 10 20
~5 0k ~5 0k
Figure 4. Driving sequence
EN
D IR
PWM
b ra kin g
GH1
G L1
GH2
Note: Before standby mode (EN = low) a braking phase is mandatory to discharge the stored energy of the motor.
G L2
10/17
L9903
Figure 5. Charging time of an external capacitor of 10nF connected to CP pin at VVS=8V and VVS=13.5V
voltage [V] 30 25 20 15 10
EN CP for VS=8V
Charging time of a 10nF load at CP
CP for VS=13.5V
5 0 0 1 2 time [ms] 3 4
Figure 6. Application Circuit Diagram
VBAT
D1
VS
10
R CP
Voltage Regulator
CS1
CS2
ST 1
+
Reference BIAS = VSTH
VCC Charge pump
11 13
CP CB1 GH1
VCC
VCC RDG
f ST
12
R
C1
Overvoltage Undervoltage Thermal shutdown V S1TH = R S1
CB1
14 S1
DG
2
M
GL1
Control Logic
EN
4
REN
19
R GL1
R
18
R GL2
GL2
R
C
DIR
5
R DIR VCC R PWM
17
V S2TH = R S2
S2
PWM
3
CB2
GH2 CB2
PR
6
Timer
15 16
R
CPR
RPR
ISO-Interface
RX
7
R RX VCC R TX = 0.5 * VVS
9
K
K-Line
TX
8
I KH
GND
20
GND
11/17
L9903
FUNCTIONAL DESCRIPTION General The L9903 integrated circuit (IC) is designed to control four external N-channel MOS transistors in H-Bridge configuration for DC-motor driving in automotive applications. It includes an ISO9141 compatible interface. A typical application is shown in fig.6. Voltage supply The IC is supplied via an external reverse battery protection diode to the VVS pin. The typical operating voltage range is down to 8V. The supply current consumption of the IC composes of static and a dynamic part. The static current is typically 5.8mA. The dynamical current Idyn is depending of the PWM frequency fPWM and the required gate charge QGate of the external power mos transistor. The current can be estimated by the expression: Idyn = 2 * fPWM * QGate An external power transistor with a gate charge of Q Gate = 160nC and a PWM frequency of fPWM = 20kHz requires a dynamical supply current of Idyn = 6.4mA. The total supply current consumption is IVS = 5.8mA + 6.4mA = 12.2mA.
Extended supply voltage range (ST) The operating battery voltage range can be extended down to 6V using the additional components shown in fig.7. A small inductor of L~150H (Ipeak~500mA) in series to the battery supply builts up a step up converter with the switching open drain output ST. The switching frequency is typical 100kHz with a fixed duty cycle of 50%. The step up converter starts below V VS < 8V, increases the supply voltage at the VS pin and switches off at VVS > 10V to avoid EME at nominal battery voltage. The diode D2 in series with the ST pin is necessary only for systems with negative battery voltage. No additional load can be driven by the step up converter. Figure 7.
L9903
VBAT
L1
D1
VS C1 C2
D2
ST
+
= VSTH
f ST
12/17
L9903
FUNCTIONAL DESCRIPTION (continued) Control inputs (EN, DIR, PWM) The cmos level inputs drive the device as shown in fig.4 and described in the truth table. The device is activated with enable input HIGH signal. For enable input floating (not connected) or VEN=0V the device is in standby mode. When activating the device a wake-up time of 50s is recommended to stabilize the internal supplies. The DIR and PWM inputs control the driver of the external H-Bridge transistors. The motor direction can be choosen with the DIR input, the duty cycle and frequency with the PWM input. Unconnected inputs are defined by internal pull up resistors. During wake-up and braking and before disactivating the IC via enable both inputs should be driven HIGH. Truth table:
Status Control inputs EN 1 2 3 4 5 6 7 8 0 1 1 1 1 1 1 1 DIR x x x x x 0 x 1 PWM x x x x x 0 1 0 TS x 1 0 0 0 0 0 0 Device status OV x 0 1 0 0 0 0 0 UV x 0 0 1 0 0 0 0 SC x 0 0 0 1 0 0 0 Driver stage for external power MOS GH1 R L L L X6) L H H GL1 R L L L X6) H L L GH2 R L L L X6) H H L GL2 R L L L X6 L L H Diagnostic DG T L L L L H H H braking mode standby mode thermal shutdown overvoltage undervoltage short circuit 6) Comment
Symbols: x Don't care 0: Logic LOW or not active 1: Logic HIGH or active
R:Resistive output L: Output in sink condition H: Output in source condition T: Tristate
TS:Thermal shutdown OV:Overvoltage UV:Undervoltage SC:Short Circuit
6. Only those external MOS transistors of the H-Bridge which are in short circuit condition are switched off. All others remain driven by DIR and PWM.
Thermal shutdown When the junction temperature exceeds TJSD all driver are switched in sink condition (L), the K- output is off and the diagnostic DG is LOW until the junction temperature drops below T JSD - TJHYST. Overvoltage Shutdown When the supply voltage VVS exceeds the overvoltage threshold V VSOVH all driver are switched in sink condition (L), the K- output is off and the diagnostic DG is LOW.
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L9903
FUNCTIONAL DESCRIPTION (continued) Undervoltage Shutdown For supply voltages below the undervoltage disable threshold the gate driver remains in sink condition (L) and the diagnostic DG is low. Short Circuit Detection The output voltage at the S1 and S2 pin of the H-Bridge is monitored by comparators to detect shorts to ground or battery. The activated external highside MOS transistor will be switched off if the voltage drop remains below the comparator threshold voltage VS1TH and VS2TH for longer than the short current detection time tSCd. The transistor remains in off condition, the diagnostic output goes LOW until the DIR or PWM input status will be changed. The status doesn't change for the other MOS transistors. The external lowside MOS transistor will be switched off if the voltage drop passes over the comparator threshold voltage VS1TH and VS2TH for longer than the short current detection time tSCd. The transistor remains in off condition, the diagnostic output goes LOW until the DIR or PWM input status will be changed. The status doesn't change for the other MOS transistors. Diagnostic Output (DG) The diagnostic output provides a real time error detection, if monitors the following error stacks: Thermal shutdown, overvoltage shutdown , undervoltage shutdown and short circuit shutdown. The open drain output with internal pull up resistor is LOW if an error is occuring. Bootstrap capacitor (CB1,CB2) To ensure, that the external power MOS transistors reach the required RDSON, a minimum gate source voltage of 5V for logic level and 10V for standard power MOS transistors has to be guaranteed. The highside transistors require a gate voltage higher than the supply voltage. This is achieved with the internal chargepump circuit in combination with the bootstrap capacitor. The bootstrap capacitor is charged, when the highside MOS transistor is OFF and the lowside is ON. When the lowside is switched OFF, the charged bootstrap capacitor is able to supply the gate driver of the highside power MOS transistor. For effective charging the values of the bootstrap capacitors should be larger than the gate-source capacitance of the power MOS and respect the required PWM ratio. Chargepump circuit (CP) The reverse battery protection can be obtained with an external N-channel MOS transistor as shown in fig.6. In this case its drain-bulk diode provides the protection. The output CP is intended to drive the gate of this transistor above the battery voltage to switch on the MOS and to bypass the drain-bulk diode with the RDSON. The CP has a connection to VS through an internal diode and a 20k resistor. Gate drivers for the external N-channel power MOS transistors (GH1, GH2, GL1, GL2) High level at EN activates the driver of the external MOS under control of the DIR and PWM inputs (see truth table and driving sequence fig.4). The external power MOS gates are connected via series resistors to the device to reduce electro magnetic emission (EME) of the system. The resistors influence the switching behaviour. They have to be choosen carefully. Too large resistors enlarge the charging and discharging time of the power MOS gate and can generate cross current in the halfbridges. The driver assures a longer switching delay time from source to sink stage in order to prevent the cross conduction. The gate source voltage is limited to 14V. The charge/discharge current is limited by the RDSON of the driver. The drivers are not protected against shorts.
14/17
L9903
FUNCTIONAL DESCRIPTION (continued) Programmable cross conduction protection The external power MOS transistors in H-Bridge ( two half bridges) configuration are switched on with an additional delay time tCCP to prevent cross conduction in the halfbridge. The cross conduction protection time tCCP is determined by the external capacitor CPR and resistor RPR at the PR pin. The capacitor CPR is charged up to the voltage limit VPRH. A level change on the control inputs DIR and PWM switches off the concerned external MOS transistor and the charging source at the PR pin. The resistor RPR discharges the capacitor CPR. The concerned external power MOS transistor will be switched on again when the voltage at PR reaches the value of VPRL. After that the CPR will be charged again. The capacitor CPR should be choosen between 100pF and 1nF. The resistor RPR should be higher than 7kW. The delay time can be expressed as follows: tCCP= RPR * CPR * ln NPR tCCP= 0.69 * RPR * CPR ISO-Interface The ISO-Interface provides the communication between the micro controller and a serial bus with a baud rate up to 60kbit/s via a single wire which is VBAT and GND compatible. The logic level transmission input TX drives the open drain K-output. The K output can be connected to a serial bus with a pull up resistor to VBAT. The Kpin is protected against overvoltage, short to GND and VS and can be driven beyond VVS and GND. During lack of VVS or GND the output shows high impedance characteristic. The open drain output RX with an internal pull up resistor monitors the status at the K-pin to read the received data and control the transmitted data. Short circuit condition at K-pin is recognized if the internal open drain transistor isn't able to pull the voltage potential at K-pin below the threshold of 0.45*VVS. Then the RX stays in high condition. A timer starts and switches the open drain transistor after typ. 20s off. A next low at the TX input resets the timer and the open drain transistor switches on again. Figure 8. Functional schematic of the ISO-interface with NPR= VPRH / VPRL = 2
RX K R RX
VCC
=
0.5 *V VS
R TX TX
I KH
R Q S
R delay T SH
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L9903
mm DIM. MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 12.6 7.4 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.3 0.51 0.32 13 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291
inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299 0.050 0.419 0.030 0.050
OUTLINE AND MECHANICAL DATA
SO20
0 (min.)8 (max.)
L
h x 45
A B e K H D A1 C
20
11 E
1
0 1
SO20MEC
16/17
L9903
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
17/17

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